Gareth Halfacree
CLEAR, a fully-open development board built around a RISC-V embedded-FPGA application-specific integrated circuit (ASIC) designed by Efabless as a showcase of what its chipIgnite platform can offer, is entering the last days of its crowdfunding campaign with just a handful of boards left to reach...
Gareth Halfacree
Zero ASIC’s chief executive Andreas Olofsson has called for “all chip designers” to try out the open-source SiliconCompiler build system, showcasing his top ten reasons for giving it a go – including a provenance feature which supports the Software Package Data Exchange (SPDX) standard. “We have...
Gareth Halfacree
Google Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective the approach could be in April last year. “Chip floorplanning is the engineering task of designing the physical layout of a...
Gareth Halfacree
The free and open source silicon community, both established and simply interested, is invited to a new event this weekend: the OpenTapeOut Conference 2021, hosted by Zero to ASIC course creator Matt Venn. “We encourage all of you folks to join us at what we hope will be the start of a revolution!...
Gareth Halfacree
Alibaba has released the source code for its XuanTie E902, E906, C906, and C910 RISC-V processor cores, promising to follow their release with additional development tools, software development kits, and customisations in the future. Designed by Alibaba’s T-Head semiconductor arm, the XuanTie C906...