YosysHQ FPGA toolchain with VHDL support
acidbourbon
TLDR I discovered that YosysHQ’s oss-cad-suite now “secretly” supports code entry not just in Verilog but also in VHDL. (Update: well I looked at older releases and VHDL support was there for a long time already – it just was not obvious to me! And I still see a lot of blog and forum posts...