implementation

Feb 15

Building A Bare-Bones 3 MB Linux Kernel For A Custom FPGA SoC

Astralvx

Disclaimer: it’s a 3.9 MB Linux kernel ; ) N.b. whilst I will try to explain concepts to those new to this field, this blog assumes a lot of fundamental knowledge on FPGAs, RTL development, Vivado, Petalinux, SOC/CPU architecture, memory managers, memory hardware, SPI NOR flash memory, reset...

serial linux verilog busybox dsp hardware embedded kernel cpu processor fpga spi fabric xilinx u-boot digilent sf schematic rtl all posts reset synthesis bootloader soc cache implementation interrupt tlb fs-boot.elf peripherals petalinux-image-minimal gpio axi bitstream systemverilog bram dtlb quad spi memory map device drivers physical address board support package nexys a7 petalinux vivado image.ub qspi soft core ddr2 mmu device tree xsdb bsp microblaze risc page tables floorplan bootm lut mig jtag utlb yocto uart rootfs virtual address boot.bin itlb pll artix-7 nexys initramfs fsbl

Aug 28 2025

Sometimes CPU cores are odd

Xe Iaso

One of the biggest lessons that I've learned in my career is that all software has bugs, and the more complicated your software gets the more complicated your bugs get. A lot of the time those bugs will be fairly obvious and easy to spot, validate, and replicate. Sometimes, the process of fixing...

implementation bugfix