processor

Feb 15

Building A Bare-Bones 3 MB Linux Kernel For A Custom FPGA SoC

Astralvx

Disclaimer: it’s a 3.9 MB Linux kernel ; ) N.b. whilst I will try to explain concepts to those new to this field, this blog assumes a lot of fundamental knowledge on FPGAs, RTL development, Vivado, Petalinux, SOC/CPU architecture, memory managers, memory hardware, SPI NOR flash memory, reset...

serial linux verilog busybox dsp hardware embedded kernel cpu processor fpga spi fabric xilinx u-boot digilent sf schematic rtl all posts reset synthesis bootloader soc cache implementation interrupt tlb fs-boot.elf peripherals petalinux-image-minimal gpio axi bitstream systemverilog bram dtlb quad spi memory map device drivers physical address board support package nexys a7 petalinux vivado image.ub qspi soft core ddr2 mmu device tree xsdb bsp microblaze risc page tables floorplan bootm lut mig jtag utlb yocto uart rootfs virtual address boot.bin itlb pll artix-7 nexys initramfs fsbl

Dec 16 2014

RISC-V Microprocessor

Logan

RISC-V is an instruction set architecture (ISA) released by UC Berkeley. Besides, a high performance, power efficient, and royalty-free open source implementation Rocket Chip is available. RISC-V was developed by Krste Asanović and David A. Patterson. In their technical report, they claimed that...

misc compiler processor